1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material having low permittivity to enhance device performance.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally, the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal and providing the electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as providing the mechanical, thermal and electrical reliability of a plurality of stacked metallization layers that may be employed on sophisticated microprocessors. Currently, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials used for replacing aluminum due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate at practical deposition rates by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called damascene or inlaid technique (single and dual) is preferably used, wherein a dielectric layer is first applied and then patterned to receive trenches and vias, which are subsequently filled with a copper-based metal.
A further major drawback of the use of copper is its propensity to readily diffuse in many dielectric materials, such as silicon dioxide, which is a well-established and approved dielectric material in fabricating integrated circuits. It is, therefore, necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid diffusion of dielectrics into the copper, thereby negatively modifying its electric characteristics, and also reducing any diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. The barrier material provided between the copper and the dielectric material should, however, in addition to the required barrier characteristics, exhibit good adhesion to the dielectric material, as well as to the copper, to impart superior mechanical stability to the interconnect, and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnection.
With the continuous shrinkage of features sizes of the circuit elements, the dimensions of the interconnects are reduced too, thereby also necessitating a reduced layer thickness of the barrier materials in interconnects so as to not unduly consume precious space of the actual metal that exhibits a considerably higher conductivity compared to the barrier material. Hence, complex barrier technologies are required to support further device scaling, wherein the usage of dielectric materials with reduced permittivity may even impart further restrictive constraints to the barrier layer, and also to preparation of exposed copper surfaces prior to applying the barrier materials, since copper readily reacts with oxygen and other reactive components, such as fluorine, sulfur and the like, which may be present in traces in the clean room ambient. Moreover, any etch byproducts created during the preceding etch process for patterning the dielectric material may also have a negative impact on the exposed copper of the underlying metal region, as will be described with reference to FIG. 1 for a typical process technique for forming sophisticated copper-based integrated circuits.
FIG. 1 depicts a schematic cross-sectional view of a semiconductor structure 100 comprising a substrate 101, for example, a semiconductor substrate bearing a plurality of individual circuit elements (not shown), such as transistors, resistors, capacitors and the like. The substrate 101 is representative of any type of appropriate substrate with or without any additional circuit elements and may, in particular, represent sophisticated integrated circuit substrates having included therein circuit elements with critical feature sizes in the deep sub-micron range. A first dielectric layer 102 is formed above the substrate 101 and includes a conductive region 104, for instance an interconnect structure comprised of a metal line 103, such as a copper line, and a first barrier layer 106 comprised of tantalum, and a second barrier layer 105 comprised of tantalum nitride. The dielectric layer 102 and the interconnect feature 104 may represent a first metallization layer. An etch stop layer 110 comprised of, for instance, silicon nitride, nitrogen-enriched silicon carbide and the like is formed above the dielectric layer 102 and partially above the copper line 103. A second dielectric layer 107 comprising at least in its upper portion 107B a dielectric material of low permittivity, as is typically used for obtaining reduced parasitic capacitances between adjacent metal lines, is formed over the etch stop layer 110 and the first dielectric layer 102 and has formed therein a trench 109 in the upper portion 107B and a via 108 in a lower portion 107A connecting to the metal line 103, thereby exposing a contamination layer 111 located on a surface portion 103A of the copper line 103. For example, the lower portion 107A may be comprised of fluorine-doped silicon dioxide deposited from TEOS, which is also referred to as FTEOS and which has a lower permittivity compared to pure TEOS silicon dioxide.
A typical process flow for forming the semiconductor structure 100 as shown in FIG. 1 may include the following steps, wherein, for the sake of simplicity, only the formation of the second metallization layer, i.e., the second dielectric layer 107 and the metal interconnect feature to be formed therein, will be described in detail as the processes for forming the interconnect feature 104 in the first dielectric layer 102 may substantially involve the same process steps. Thus, after planarizing the dielectric layer 102, including the inter-connect feature 104, and forming the etch stop layer 110, thereby passivating the interconnect structure 104, as pure copper forms a highly reactive surface, the dielectric layer 107 is deposited by well-known deposition methods, such as plasma-enhanced CVD, spin-on techniques and the like, wherein, as previously pointed out, silicon dioxide including fluorine deposited from TEOS by CVD is frequently employed. Subsequently, the dielectric layer 107 is patterned by well-known photolithography and anisotropic etch techniques, wherein an intermediate etch stop layer (not shown) may be used in patterning the trench 109. It should further be noted that different approaches may be employed in forming the trench 109 and the via 108, such as a so-called via first trench last approach, or a trench first via last approach, or, in other approaches, the via 108 may be formed first and filled with metal prior to the formation of the trench 109. In the present example, a so-called dual damascene technique is described in which the trench 109 and the via 108 are simultaneously filled with metal.
Irrespective of the etch scheme used, in the last etch step for forming the via 108, the etch stop layer 110 is opened and the copper surface 103A is exposed to the reactive etch ambient, which may contain fluorine, in particular when the dielectric layer 107 also comprises fluorine. As a consequence, the contamination layer 111 containing a copper/fluorine/oxygen compound may be formed on the surface portion 103A. Since the contamination layer 111 may significantly affect the further processes, such as the formation of a barrier layer and seed layer for the subsequent copper fill process, via reliability is reduced and product yield is lowered. The contamination layer 111 is typically removed by a wet chemical etch process on the basis of, for example, diluted fluoric acid (HF) or other appropriate chemicals. It has been found that, during this wet chemical process, the contamination layer 111 is effectively removed yet the surface portion 103A is again exposed to a reactive environment, thereby resulting in a recreation of a contamination layer having a similar negative effect on the further processing as the layer 111.
Moreover, in sophisticated applications, the dielectric layer 107 may comprise sensitive dielectric materials having a dielectric constant of 2.7 and less, which may frequently be referred to as ultra low-k (ULK) dielectrics, which may also be affected by a wet chemical process, thereby resulting in any process non-uniformities during the further processing, for instance by depositing a conductive barrier material and a seed layer, depending on the corresponding process strategy. Furthermore, the metal region 104 may comprise, in addition to the etch stop layer 110, a conductive cap layer in advanced applications in view of enhancing overall electromigration behavior of the metal region 104. To this end, well-established metal alloys, such as cobalt/tungsten/phosphorous (COWP) and the like, may be used in this case which, however, may be removed during the corresponding wet chemical etch process. Thus, in many cases, even under-etched areas may be created at lower sidewall portions of the via opening 108, which may result in a significant contact deterioration and which may require sophisticated process techniques, such as wet chemical etch processes on the basis of sophisticated chemistries and/or corresponding techniques for refilling any under-etched areas by an additional deposition process. On the other hand, the exposed copper-containing surface of the metal region 104 may be exposed due to reactive components that may be present in the ambient atmosphere, even after performing the corresponding wet chemical etch process, thereby requiring further cleaning steps, for instance, prior to forming a conductive barrier layer and the like wherein, however, the more or less aggressive chemicals used during the preceding cleaning process may result in a certain degree of surface modification, thereby contributing to further process non-uniformities which may finally result in reduced contact reliability or production yield.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.